Department of Computer Science, University of Crete, Greece

CS-534: Packet Switch Architecture

Spring 2007
Manolis Katevenis
  • Bibliography.
  • Course Description [PDF] - old Schedule (2006 and older)

    Lecture Notes, Transparencies, Exercises:

    ACACES 2007 (Third International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems) Slides for the course on "Queue and Flow Control Architectures for Interconnection Switches", by Manolis Katevenis, in PDF:
    1. [Slides] [Handouts] Basic Concepts and Queueing Architectures
    2. [Slides] [Handouts] High-Throughput Multi-Queue Memories
    3. [Slides] [Handouts] Crossbars, Scheduling, and Combination Queueing
    4. [Slides] [Handouts] Flow and Congestion Control in Switching Fabrics

    This Year:

    Chapter 0: Introduction

    Chapter 1: Transmission Links, Multiplexing
    Chapter 2: Buffer Memory Technology and Time Switching
    Chapter 3: Multi-Queue Memory Management for Shared-Buffer Switching
    Chapter 4: Time-Space Switching and Input Queueing Architectures
    Chapter 5: Switching Fabrics, Inverse Multiplexing
    Chapter 6: Flow Control in Buffered Switching Fabrics
    Chapter 7: Output Scheduling for Quality-of-Service (QoS) Guarantees
    Other Topics: Please refer to the bibliography pointed below (2003 and older)

    Previous Years:

  • Spring 2006
  • Spring 2005 (last year with slides in HTML - GIF - JPEG format)
  • Previous Years Home Pages: Sp. 2004 - Sp. 2003 - Fall 2001 - Sp. 2000 and older.
    © copyright University of Crete, Greece. Last updated: 13 July 2007 by M. Katevenis.