CS-425: Computer Systems Architecture
Department of Computer Science, University of Crete
AMD quad-core processor, courtesy of AMD Class meets Monday, Wednesday, 13.15–15.00 in room Rho Alpha 203 (Knossos campus). Friday classes will be held as needed at the same time in Rho Alpha 203, to make up in case of instructor's absence during regular class meeting times.

Midterm scheduled during the week between November 14 and November 18. The midterm will be organized as a take-home exam.

Home   Syllabus   Lectures   Assignments   Personnel 

Textbook and Reading Material
H&P: Computer Architecture, 3rd Edition
Course textbook: Hennessy and Patterson, Computer Architecture, A Quantitative Approach, 3rd Edition. Available in Greek (Tziolas publishers, translation by D. Pnevmatikatos, D. Serpanos and G. Stamoulis). ISBN 9789604180769.

Additional reading: Shen and Lipasti, Modern Processor Design, Fundamentals of Superscalar Processors, McGraw Hill, 2005, ISBN 0-07-059033-8.
Additional reading material will be posted as needed, during classes. Reading material includes Chapters from other textbooks (in English) and technical papers from conferences or journals covering the field of Computer Architecture.

Lectures

Class Topic Slides Reading listAssignments
5/10 Welcome and introduction Slides,handout 2up, handout 4up, updated on Oct 13, 17:24 Chapter 1 from course textbook
7/10 Pipelining review Slides,handout 2up, handout 4up, updated on Oct. 13, 17:24 Appendix A, A.1–A.3 from course textbook
10/10 Hazards, Introduction to ILP techniques Handout on 7/10 Appendix A, A.4 from course textbook
12/10 ILP and instruction scheduling. ScoreboardSlides, handout 2up, handout 4up, updated on Oct. 08, 11:28Chapter 3, section 3.1 from course textbookHomework 1, updated Oct. 13, 17:28
14/10 Dynamic scheduling with scoreboardHandout of 6/10Chapter 3, section 3.2–3.3 from course textbook, CDC 6600 original scoreboard design paper
17/10 Dynamic scheduling with Tomasulo's algorithmSlides, handout 2up, handout 4up, updated on Oct. 11, 11:55Tomasulo's original paper
19/10 Branch prediction Slides, handout 2up, handout 4up, updated on Oct. 21, 12:02Chapter 3, Section 3.4 from course textbook
21/10 Branch prediction (correlation, jumps). Multiple-IssueHandout on 19/10Chapter 3, Sections 3.4–3.5 from course textbook, Alternative implementations of two-level adaptive branch predictors Homework 2, updated Oct 21, 12:03
24/10 Multiple issue processors (statically and dynamically scheduled) Slides, handout 2up, handout 4up, updated on Oct. 31, 08:18Chapter 3, Section 3.6 from course textbook, Chapter 5, Section 5.1 from book “Modern Processor Design: Fundamentals of Superscalar Processors”, by Lipasti and Shen
26/10 SpeculationSlides, handout 2up, handout 4up, updated on Oct. 31, 08:19Chapter 3, Section 3.7 from course textbook, Chapter 5, Sections 5.2–5.3 from book “Modern Processor Design: Fundamentals of Superscalar Processors”, by Lipasti and Shen
31/10 Limits of ILPSlides, handout 2up, handout 4up, updated on Oct. 31, 19:44Chapter 3, Sections 3.8–3.10 from course textbook, Limits of Instruction-Level Parallelism, by David Wall, WRL Research Report 93/6Programming Assignment 1, updated Oct. 31 19:45
2/11 Software techniques for ILP: Static scheduling and VLIW Slides, handout 2up, handout 4up, updated on Nov. 4, 21:36Chapter 4, Sections 4.1–4.3 from course textbook
7/11 Software pipelining. Introduction to vector processorsSlides, handout 2up, handout 4up, updated on Nov. 23, 21:22 reading material from previous lecture, Appendix F from book Computer Architecture: A Quantitative Approach, Fourth Edition, by Hennessy and Patterson Homework 3, updated Nov. 7, 20:43
21/11 Simultaneous Multithreading.Slides, handout 2up, handout 4up, updated on Nov. 21, 14:20 reading material from previous lecture, Chapter 3, Section 3.5, from textbook Computer Architecture: A Quantitative Approach, Fourth Edition, by Hennessy and Patterson, Simultaneous Multithreading: Maximizing On-Chip Parallelism, Tullsen, Eggers and Levy, ISCA'95, Power5 System Microarchitecture, Sinharoy et. al, IBM Journal of Research and Development, 49(4–5), September 2005.
23/11 Cache memories: Design and performance analysisSlides, handout 2up, handout 4up, updated on November 28, 11:27 Chapter 5, Sections 5.1–5.3, from textbook Computer Architecture: A Quantitative Approach, Third Edition, by Hennessy and Patterson
25/11 Cache design optimizationsSlides, handout 2up, handout 4up, updated on Nov. 25, 22:49 Chapter 5, Sections 5.4–5.7, from textbook Computer Architecture: A Quantitative Approach, Third Edition, by Hennessy and Patterson
28/11 Software transformations for localitylecture notes from 25/11 Chapter 5, Section 5.3, from textbook Computer Architecture: A Quantitative Approach, Second Edition, by Hennessy and Patterson Homework 4, updated 28/11, 11:33
30/11 Hardware prefetchingSlides, handout 2up, handout 4up, updated on Nov. 26, 15:11 Chapter 3, Section 3.1, from textbook Memory Systems: Cache, DRAM, Disk, by Jacob, Ng, and Wang
2/12 Software prefetching. DRAM TechnologiesLecture slides from 30/11
5/12 DRAM TechnologiesSlides, handout 2up, handout 4up, updated on Dec. 1, 12:00 Chapter 7, Sections 7.1–7.5, from textbook Memory Systems: Cache, DRAM, Disk, by Bruce Jacob, Spencer W. Ng, and David T. Wang
7/12 Multiprocessor ArchitecturesSlides, handout 2up, handout 4up, updated on Jan. 12 2011, 01:03 Chapter 6, Sections 6.1–6.2, from textbook Computer Architecture: A Quantitative Approach, Third Edition Programming Assignment 2, updated Dec. 14, 12:40

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