CS425: Computer Systems Architecture (Fall 2018)
Department of Computer Science, University of Crete
Schedule
Class hours: Monday and Wednesday 16.15 - 18.00 in room H.204
Friday classes will be held as needed in room H.206 (16:15 - 18:00) to make up in case of instructor's absence during regular class meeting times.
Office hours: Monday 14:15 - 16:00 @ K319 (preferably by appointment)
Staff
| Instructor(s) | Teaching Assistant(s) |
| Dr. Vassilis Papaefstathiou | Mr. Evangelos Mageiropoulos |
Course Information
| Area: | Hardware and Computer Systems (E4) |
| Description: | Performance metrics, pipelining and hazards, dynamic instruction scheduling with scoreboard and Tomasulo, ILP and static instruction scheduling, branch prediction, precise exceptions, speculation, multiple issue out-of-order superscalar processors, VLIW processors, thread level paralellism and multithreaded processors, multi-level cache memories and design optimizations, virtual memory and TLBs, multicore processors, snoop-based cache coherence, memory consistency, DRAM main memory technologies. |
| ECTS: | 6 |
| Prerequisites: | CS225 Computer Organization |
| Grading: |
Homeworks/Assignments: 35% (grade must be > 4.5)
Midterm Exam: 20% (mandatory) Final Exam: 45% (grade must be > 4.5) |
| Mailing-list: | hy425-list at csd dot uoc dot gr |
Textbook and Reading Material
Course textbook: Hennessy and Patterson, Computer Architecture, A Quantitative Approach, 4th Edition. Available in Greek (Tziolas publishers, translation by D. Pnevmatikatos, D. Serpanos and G. Stamoulis). ISBN 9789604180769.
Additional reading: Shen and Lipasti, Modern Processor Design, Fundamentals of Superscalar Processors, McGraw Hill, 2005, ISBN 0-07-059033-8.
Additional reading material will be posted as needed, during classes. Reading material includes Chapters from other textbooks (in English) and technical papers from conferences or journals covering the field of Computer Architecture.
Lectures Schedule and Material
| Date | Description | Material | Reading List |
|---|---|---|---|
| Sep. 24 | Welcome and Introduction | Slides | Chapter 1 (1.1 - 1.3) from course textbook |
| Sep. 26 | Metrics | Slides | Chapter 1 (1.4 - 1.12) from course textbook |
| Oct. 1 | Pipelining Review | Slides | Appendix A (A.1 - A.3) from course textbook |
| Oct. 3 | Pipelining Review | Slides from Oct. 1 | |
| Oct. 8 | Dynamic Instruction Scheduling: Scoreboard | Slides | Section 2.1, Appendix A (A.5, A.7, A.8) from course textbook |
| Oct. 10 | Dynamic Instruction Scheduling: Scoreboard | Slides from Oct. 8 | CDC 6600 original scoreboard design paper |
| Oct. 15 | Dynamic Instruction Scheduling: Tomasulo | Slides | Chapter 2 (2.4, 2.5) from course textbook |
| Oct. 17 | Dynamic Instruction Scheduling: Tomasulo | Slides from Oct. 15 | Tomasulo's original paper |
| Oct. 22 | Static Instruction Scheduling | Slides | Section 2.2, Appendix G (G.1 - G.3) from course textbook |
| Oct. 24 | Static Instruction Scheduling | Slides from Oct. 22 | |
| Nov. 02 | Branch Prediction | Slides | Sections 2.3, 2.9 (pages 121-126), Appendix G (G.4) from course textbook. |
| Nov. 05 | Branch Prediction | Slides from Nov. 02 |
1. Alternative implementations of two-level adaptive branch predictors
2. Combining branch predictors |
| Nov. 07 | Reorder Buffer, Precise Exceptions and Speculation | Slides | Appendix A (A.4), Section 2.6, Section 2.9 (pages 127-129) from course textbook |
| Nov. 12 | Reorder Buffer, Precise Exceptions and Speculation | Slides from Nov. 07 | |
| Nov. 14 | Multiple Issue Processors: Superscalar and VLIW | Slides | Sections 2.7, 2.8, Appendix G.3 (G-19 to G-21), Appendix G.6 |
| Nov. 19 | Multiple Issue Processors: Superscalar and VLIW | Slides from Nov. 14 | Limits of Instruction-Level Parallelism |
| Nov. 21 | Solutions for Homeworks 1 and 2 (E. Mageiropoulos) | Homework 1 , Homework 2 | |
| Nov. 28 | Midterm Examination (mandatory 20%) | All lectures up to Branch Prediction (inclusive) | |
| Nov. 30 | Thread-Level Parallelism (TLP) | Slides | Sections 3.5, 3.6 |
| Dec. 3 | Thread-Level Parallelism (TLP) | Slides from Nov. 30 | |
| Dec. 5 | Cache memories: Design and performance analysis | Slides | Section 5.1, Appendix C.1 |
| Dec. 7 | Cache memories: Design and performance analysis | Slides from Dec. 5 | |
| Dec. 10 | Cache design optimizations | Slides | Section 5.2, Appendix C.2 |
| Dec. 12 | Cache design optimizations | Slides from Dec. 10 | |
| Dec. 14 | Multi-core Processors (Basics) | Slides | Chapter 4 |
| Dec. 17 | Snoop-based Cache Coherence | Slides | Chapter 4 |
| Jan. 16 | Final Examination (mandatory 45%) | Wednesday, January 16th 2019: 17.00 - 20.00 Room A.121 |
Websites from Previous Years
- Fall 2017 (taught by V. Papaefstathiou)
- Fall 2016 (taught by V. Papaefstathiou and I. Mavroidis)
- Fall 2015 (taught by I. Mavroidis)
- Fall 2014 (taught by I. Mavroidis)
- Fall 2013 (taught by C. Sotiriou and I. Mavroidis)
- Fall 2012 (taught by C. Sotiriou and I. Mavroidis)
- Fall 2011 (taught by D. Nikolopoulos)
- Fall 2008
- Spring 2008
- Spring 2002 (taught by C. Sotiriou)
Last update: 14 Dec. 2018 - by V. Papaefstathiou