CS-425: Computer Systems Architecture
Department of Computer Science, University of Crete
AMD quad-core processor, courtesy of AMD Class meets Monday, Wednesday, 12.15–14.00 in room A.121. Friday classes will be held as needed at the same time in A.121, to make up in case of instructor's absence during regular class meeting times.

Announcemens
Home   Syllabus   Lectures   Assignments   Personnel 

Textbook and Reading Material
H&P: Computer Architecture, 4th Edition
Course textbook: Hennessy and Patterson, Computer Architecture, A Quantitative Approach, 4th Edition. Available in Greek (Tziolas publishers, translation by D. Pnevmatikatos, D. Serpanos and G. Stamoulis). ISBN 9789604180769.

Additional reading: Shen and Lipasti, Modern Processor Design, Fundamentals of Superscalar Processors, McGraw Hill, 2005, ISBN 0-07-059033-8.
Additional reading material will be posted as needed, during classes. Reading material includes Chapters from other textbooks (in English) and technical papers from conferences or journals covering the field of Computer Architecture.

Lectures

Class Topic Slides Reading list Assignments
25/9 Welcome and introduction Slides Chapter 1 (1.1-1.3) from course textbook
2/9 Metrics Slides Chapter 1 (1.4-1.12) from course textbook
7/9 Pipelining review Slides Appendix A (A.1-A.3) from course textbook
12/10 Pipelining review Handouts from 14/10 Homework 1
14/10 Dynamic scheduling with Scoreboard Slides Section 2.1, Appendix A (A.5, A.7,A.8) from course textbook
19/10 Dynamic scheduling with Scoreboard Handouts from 14/10
21/10 Dynamic scheduling with Tomasulo Slides Chapter 2 (2.4,2.5) from course textbook
26/10 Dynamic scheduling with Tomasulo Handouts from 25/10 Tomasulo's original paper
2/11 ILP and Static scheduling Slides Section 2.2, Appendix G(G.1-G.3) from course textbook Homework 2
9/11 Branch prediction Slides Sections 2.3, 2.9 (pages 121-126), Appendix G(G.4) from course textbook. Alternative implementations of two-level adaptive branch predictors
11/11 Precise Exceptions and Speculation Slides Appendix A(A.4), Section 2.6, Section 2.9 (pages 127-129) from course textbook
16/11 Precise Exceptions and Speculation Handouts from 13/11 Programming Assignment 1
18/11 Multiple issue processors (Superscalar and VLIW) Slides Sections 2.7, 2.8, Appendix G.3(G-19 to G-21), Appendix G.6
23/11 Thread-Level Parallelism (TLP) Slides Sections 3.5, 3.6,Simultaneous Multithreading: Maximizing On-Chip Parallelism, Tullsen, Eggers and Levy, ISCA'95, Power5 System Microarchitecture, Sinharoy et. al, IBM Journal of Research and Development, 49(4–5), September 2005.
25/11 Cache memories: Design and performance analysis Slides Section 5.1, Appendix C.1
30/11 Cache memories Handouts from 1/12 Homework 3
2/12 Cache design optimizations Slides Appendix C.2, Section 5.2
7/12 Cache design optimizations Handouts from 3/12
9/12 Virtual memory Slides Appendix C.4 Programming Assignment 2
14/12 Main Memory Slides Chapter 7, Sections 7.1–7.5, from textbook Memory Systems: Cache, DRAM, Disk, by Bruce Jacob, Spencer W. Ng, and David T. Wang
16/12 Multi-core Processors (Basics) Slides Chapter 4

Websites from previous years:

I. Mavroidis - Last Modification - 1/10/2014.