CS425: Computer Systems Architecture (Fall 2017)

Department of Computer Science, University of Crete

Schedule

Class hours: Monday and Wednesday 16.15 - 18.00 in room H.204

Office hours: By Appointment

Staff

Instructor(s) Teaching Assistant(s)
Dr. Vassilis Papaefstathiou Mr. Leandros Tzanakis-Arnaoutakis
Prof. Manolis Katevenis

Course Information

Area: Hardware and Computer Systems (E4)
Description: Performance metrics, pipelining and hazards, dynamic instruction scheduling with scoreboard and Tomasulo, ILP and static instruction scheduling, branch prediction, precise exceptions, speculation, multiple issue out-of-order superscalar processors, VLIW processors, thread level paralellism and multithreaded processors, multi-level cache memories and design optimizations, virtual memory and TLBs, multicore processors, snoop-based cache coherence, memory consistency, DRAM main memory technologies.
ECTS: 6
Prerequisites: CS225 Computer Organization
Grading: Homeworks/Assignments: 35% (grade must be > 4.5)
Midterm Exam: 20% (mandatory)
Final Exam: 45% (grade must be > 4.5)
Mailing-list: hy425-list at csd dot uoc dot gr

Textbook and Reading Material

Computer Architecture, A Quantitative Approach

Course textbook: Hennessy and Patterson, Computer Architecture, A Quantitative Approach, 4th Edition. Available in Greek (Tziolas publishers, translation by D. Pnevmatikatos, D. Serpanos and G. Stamoulis). ISBN 9789604180769.

Additional reading: Shen and Lipasti, Modern Processor Design, Fundamentals of Superscalar Processors, McGraw Hill, 2005, ISBN 0-07-059033-8.

Additional reading material will be posted as needed, during classes. Reading material includes Chapters from other textbooks (in English) and technical papers from conferences or journals covering the field of Computer Architecture.

Lectures Schedule and Material

Date Description Material Reading List
Sep. 25 Welcome and Introduction Slides Chapter 1 (1.1 - 1.3) from course textbook
Sep. 27 Metrics Slides Chapter 1 (1.4 - 1.12) from course textbook
Oct. 2 Pipelining Review Slides Appendix A (A.1 - A.3) from course textbook
Oct. 4 Pipelining Review Slides from Oct. 2
Oct. 9 Dynamic Instruction Scheduling: Scoreboard Slides Section 2.1, Appendix A (A.5, A.7, A.8) from course textbook
Oct. 11 Dynamic Instruction Scheduling: Scoreboard Slides from Oct. 9 CDC 6600 original scoreboard design paper
Oct. 16 Dynamic Instruction Scheduling: Tomasulo Slides Chapter 2 (2.4, 2.5) from course textbook
Oct. 23 Dynamic Instruction Scheduling: Tomasulo Slides from Oct. 16 Tomasulo's original paper
Oct. 25 Static Instruction Scheduling Slides Section 2.2, Appendix G (G.1 - G.3) from course textbook
Oct. 30 Branch Prediction Slides Sections 2.3, 2.9 (pages 121-126), Appendix G (G.4) from course textbook.
Nov. 1 Branch Prediction Slides from Oct. 30 Alternative implementations of two-level adaptive branch predictors
Nov. 6 Reorder Buffer, Precise Exceptions and Speculation Slides Appendix A (A.4), Section 2.6, Section 2.9 (pages 127-129) from course textbook
Nov. 8 Reorder Buffer, Precise Exceptions and Speculation Slides from Nov. 6
Nov. 13 Multiple Issue Processors: Superscalar and VLIW Slides Sections 2.7, 2.8, Appendix G.3 (G-19 to G-21), Appendix G.6
Nov. 15 Solutions for Homeworks 1 and 2 (L. Tzanakis)
Nov. 20 Multiple Issue Processors: Superscalar and VLIW Slides from Nov. 13 Limits of Instruction-Level Parallelism
Nov. 22 Midterm Examination (mandatory 20%) All lectures up to Branch Prediction (inclusive)
Nov. 27 Thread-Level Parallelism (TLP) Slides Sections 3.5, 3.6
Nov. 29 Thread-Level Parallelism (TLP) Slides from Nov. 27 Simultaneous Multithreading: Maximizing On-Chip Parallelism
Power5 System Microarchitecture
Dec. 4 Cache memories: Design and performance analysis Slides Section 5.1, Appendix C.1
Dec. 6 Cache memories: Design and performance analysis Slides from Dec. 4
Dec. 8 Cache design optimizations Slides Section 5.2, Appendix C.2
Dec. 11 Cache design optimizations Slides from Dec. 8
Dec. 13 Multi-core Processors (Basics) Slides Chapter 4
Dec. 15 Snoop-based Cache Coherence Slides Chapter 4
Dec. 18 Discussion of Homeworks and Prog. Assignments (L. Tzanakis)
Dec. 20 Snoop-based Cache Coherence Slides from Dec. 15
Dec. 22 Virtual Memory Slides Appendix C.4
Jan. 17 Final Examination (mandatory 45%) Wednesday, January 17th 2018: 17.00 - 20.00 Room H.204

Homeworks and Assignments

Date Description Material Deadline
Oct. 6 Homework 1 HW Oct. 16, 23:59
Oct. 30 Homework 2 HW Nov. 10, 23:59
Nov. 18 Programming Assignment 1 PA Dec. 4, 23:59
Dec. 1 Homework 3 HW Dec. 13, 23:59
Dec. 13 Programming Assignment 2 PA Jan. 8 2018, 23:59

Websites from Previous Years

Last update: 5 Jan. 2018 - by V. Papaefstathiou