Chapter 2:
Link and Memory Architectures and Technology
2.1
Links, Throughput/Buffering, Multi-Access Overheads
[Slides in PDF]
[Slides Handout in PDF]
[reminder for 09a: possibly move "cut-through" from 3.1 to 2.1;
Older text for section 2.1.1:
[Text in HTML]
[Text in PDF] ]
3.3, 3.4
Multiple Queues within a Buffer Memory, Queueing for Multicast Traffic
[Slides in PDF]
[Slides Handout in PDF]
[animated PPT
for queue operations with free-block preallocation]
ACACES 2007
(Third International Summer School on
Advanced Computer Architecture and Compilation for Embedded Systems)
Slides for the course on
"Queue and Flow Control Architectures for Interconnection Switches",
by Manolis Katevenis, in PDF:
[Slides]
[Handouts]
Flow and Congestion Control in Switching Fabrics
Chapter 7:
Output Scheduling for Quality-of-Service (QoS) Guarantees