Patents and Publications

- Patents:

  • Michalis Christofilopoulos, Pavlos M. Mattheakis and Christos P. Sotiriou, “Apparatus and method for mixed single-rail and dual-rail combinational logic with completion detection”, US Patent No: 8,074,193, Dec, 2011 .
  • Pavlos M. Mattheakis and Christos P. Sotiriou, “Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same”, US Patent No: 7,603,635, Oct, 2009 .

- Papers in Journals (2012-...):

  • I. Seitanidis, G. Dimitrakopoulos, P. M. Mattheakis, L. Masse-Navette and D. Chinnery, “ Timing-Driven and Placement-Aware Multi-Bit Register Composition”, to appear in IEEE Transactions on Computer Aided Design (TCAD), 2018.
  • N. Tampouratzis, P. M. Mattheakis and I. Papaefstathiou, “Accelerating Intercommunication in Highly Parallel Systems”, ACM Transactions on Architecture and Code Optimization (TACO), 2016.
    • invited presentation in 11th International Conference on High Performance and Embedded Architectures and Compilters (HiPEAC), Stockholm, Sweeden, EU, January 2017.
  • S. Roy, P.Mattheakis, D. Z. Pan and L. Masse-Navette, “Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure”, IEEE Transactions on Computer Aided Design (TCAD), 2015.
  • P. Mattheakis and I. Papaefstathiou, “Significantly reducing MPI intercommunication latency and power overhead in both Embedded and HPC systems”, ACM Transactions on Architecture and Code Optimization (TACO), 2013.
    • invited presentation 8th International Conference on High Performance and Embedded Architectures and Compilters (HiPEAC), Berlin, Germany, EU, January 2013. Presentation

- Papers in Conferences (2012-...):

  • I. Seitanidis, G. Dimitrakopoulos, P. Mattheakis, L. Masse-Navette, D. Chinnery , “Timing Driven Incremental Multi-Bit Register Composition Using a Placement Aware ILP formulation”, ACM/IEEE Design Automation Conference (DAC), USA, June 2017.(acc. rate 17%)
  • Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos and Giorgos Dimitrakopoulos, “A Low Power Network On Chip Architecture for Tile-based Chip Multiprocessors”, IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI), Boston, USA, May 2016.(acc. rate 25%)
  • Subhendu Roy, Pavlos M. Mattheakis, Peter Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet and David Z. Pan, “Skew Bounded Buffer Tree Resynthesis for Clock Power Optimization”, IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, Pennsylvania, USA, May 2015.(acc. rate 28%)
  • Subhendu Roy, Pavlos M. Mattheakis, David Z. Pan and Laurent Masse-Navette “Evolving Challenges and Techniques for Nanometer SoC Clock Network Synthesis”, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), China, October 2014. (Invited Paper)
  • Subhendu Roy, Pavlos M. Mattheakis, David Z. Pan and Laurent Masse-Navette “Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure”, ACM International Symposium on Pysical Design (ISPD), Petaluma, CA, USA, March 2014. (acc. rate 31%) (Best Paper Award) Presentation
  • G. Dimitrakopoulos, I. Seitanidis, A. Psarras, K. Tsiouris, P. M. Mattheakis and J. Cortadella “Hardware Primitives for the Synthesis of Multithreaded Elastic Systems”, ACM International Conference on Design and Test in Europe (DATE), Dresden, Germany, EU, March 2014.(acc. rate 21%)
  • Pavlos M. Mattheakis and Christos P. Sotiriou “Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications based on Burst-Mode FSM Decomposition”, IEEE 26th International Conference on VLSI Design (VLSID), Pune, India, January 2013.(acc. rate 21%) Presentation
  • Pavlos M. Mattheakis, Christos P. Sotiriou and Peter A. Beerel “A Polynomial Time Flow for Implementing Free-Choice Petri-Nets”, 30th IEEE International Conference on Computer Design (ICCD), Montreal, Canada, October 2012.(acc. rate 25%) Presentation

- Papers in Refereed Workshops:

  • Michalis Christofilopoulos, Pavlos M. Mattheakis and Christos P. Sotiriou “Indicating Circuits with Area, Delay Tradeoffs”, 19th International Workshop on Logic & Synthesis (IWLS) 2010, Irvine, CA, USA, June 2010.

- Technical Reports/Theses:


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