Assembly language and machine language;
example: the basic RISC-V Instruction Set.
Elementary Assembly programming:
if-then-else, loops, arrays, pointers,
and introduction to the run-time stack, procedure calls,
and caller/callee-saved registers.
Processor implementation using
registers, multiplexors, adders, ALU's, memories, and combinatorial logic.
Datapath and control unit design.
Interrupts-exceptions.
Pipelining: the classical 5-stage in-order pipeline,
with dependence detection and internal forwarding.
Processor performance, CPI and related equations.
Memory System:
introduction to Cache memories.
Virtual memory.
User-kernel mode, system call, protection.
Peripheral devices
and their communication with the central unit.
Memory-mapped I/O.
Polling, interrupts, DMA.
Design and simulation visualization
for a subset of a RISC-V processor at the register transfer level,
in single-cycle and 5-stage pipelined versions.
processor performance, memory (cache, virtual), and I/O exercises,
including the use of a simple cache simulator.
Book:
D. Patterson, J. Hennessy:
"Computer Organization and Design – RISC-V Edition",
2017, Elsevier Morgan Kaufmann Series, ISBN 9780128122754:
large parts of chapters 2, 4, 5, plus other topics.