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My research interests include: Parallel Computer Architecture, Memory Hierarchies, High-Performance Computing, Hardware-accelerated Machine Learning and AI, High-Speed Interconnects, Low-Power and Embedded Systems.

I regularly participate in conference program committees and list (not exhaustive) recent and upcoming activities:

• SC 2026, Member of the Program Committee (Architecture and Networks)
• ICS 2026, Member of the Program Committee
• IPDPS 2026, 2019, Member of the Program Committee (Architecture Track)
• HPCA 2025, Member of the Program Committee
• SAMOS 2025, Member of the Program Committee
• FPL 2024, 2019, PhD Forum and Demo Night Co-Chair
• FPL 2024, 2023, 2021, 2020, 2019, Member of the Program Committee
• MICRO 2023, 2022, 2021, 2020, Member of the External Program Committee
• CLUSTER 2019, Member of the Program Committee (Area: Architecture, Network/Communications, and Management)
• PACT 2018, Member of the Program Committee

I am currently teaching the following courses:

• CS220: Digital Circuits Lab
• CS425: Computer Systems Architecture
• CS523: Digital Circuits Design Lab using EDA Tools

Vassilis Papaefstathiou (male) is an Assistant Professor of Computer Science at the University of Crete and FORTH-ICS, Greece. He received his Ph.D. in Computer Science (2013) from the University of Crete. From 2014 – 2016 he was a Postdoctoral Researcher at Chalmers University of Technology, Sweden and worked on the prestigious ERC Advanced Grant project MECCA. He has experience on industrial IC Design and Verification and has worked with ISD S.A. and closely with ST Microelectronics (2001-2003). His research interests include Parallel Computer Architecture, Memory Hierarchies, High-Performance Computing, Hardware-accelerated Machine Learning and AI, High-Speed Interconnects, Low-Power and Embedded Systems, with particular emphasis on cross-layer design and optimization. He has published more than 50 papers in peer-reviewed conferences such as: HPCA, ICS, IPDPS, NOCS, INFOCOM, CCS and journals such as: ACM TACO, IEEE Micro, and IEEE ToN. He has also participated in numerous conference program committees including HPCA, MICRO, IPDPS, PACT, FPL. He has been involved in several EU-funded research projects (DARE-SGA1, EPI-SGA1, EPI-SGA2, EUPILOT, RISER, eProcessor, Plasma-PEPSC CoE, Space CoE, dAIEDGE, EuroEXA, ExaNest, ExaNoDe, ECOSCALE, EuroServer, ERC MECCA, SHARCS, ENCORE, SARC, UNISIX, SIVSS) and has led the design of several ASIC and FPGA-based hardware prototypes for multicore architectures and high-performance interconnects. He coordinated FORTH’s tasks in European Processor Initiative - Phase 1 (EPI-SGA1 2019-2021) and led FORTH's technical contributions on hardware design for the EPAC RISC-V chip and the EPAC chip bring-up and testing. He is the Principal Investigator of FORTH for the European Processor Initiative – Phase 2 (EPI-SGA2 2022 – 2025), The European Pilot (2021 – 2026), DARE-SGA1 (2025-2028), eProcessor (2021 – 2025), and Plasma-PEPSC (2023 – 2026). He is also actively involved in the Task Groups and SIGs of the RISC-V Foundation and served as the first Acting Chair of the RISC-V IOMMU Task Group.

Journal Papers

• J17 Manolis Ploumidis, Fabien Chaix, Nikolaos Chrysos, Marios Assiminakis, Nikolaos Kallimanis, Nikolaos Kossifidis, Michael Nikoloudakis, Nikolaos Dimou, Michalis Gianioudis, George Ieronymakis, Aggelos Ioannou, George Kalokerinos, Pantelis Xirouchakis, Astrinos Damianakis, Michael Ligerakis, Theocharis Vavouris, Manolis Katevenis, Vassilis Papaefstathiou, Manolis Marazakis, and Iakovos Mavroidis, “The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 18, Issue 2, April 2025.
• J16 Antonis Psistakis, Nikos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Gianioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou, and Manolis Katevenis, “Optimized Page Fault Handling During RDMA”, IEEE Transactions on Parallel and Distributed Systems (TPDS), Volume 33, Issue 12, December 2022.
• J15 Ahsen Ejaz, Vassilis Papaefstathiou, and Ioannis Sourdis, “HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers”, IEEE/ACM Transactions on Networking (ToN), Volume 29, Issue 1, February 2021.
• J14 George Christou, Giorgos Vasiliadis, Vassilis Papaefstathiou, Antonis Papadogiannakis, and Sotiris Ioannidis, “On Architectural Support for Instruction Set Randomization”, ACM Transactions on Architecture and Code Optimization (TACO), Volume 17, Issue 4, November 2020.
• J13 Aggelos Ioannou, Konstantinos Georgopoulos, Pavlos Malakonakis, Dionisios Pnevmatikatos, Vassilis Papaefstathiou, Ioannis Papaefstathiou, Iakovos Mavroidis, “UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 13, Issue 4, September 2020.
• J12 David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Francesco Simula, Antonio Ragagnin, Luca Tornatore, Igor Coretti, and Giuliano Taffoni “Performance and Energy Footprint Assessment of FPGAs and GPUs on HPC Systems Using Astrophysics Application”, Computation, Volume 8, Issue 2, April 2020.
• J11 Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, and Ioannis Sourdis, “Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache”, ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 4, January 2019.
• J10 Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, and Per Stenström, “Global Dead-Block Management for Task-Parallel Programs”, ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 3, August 2018.
• J9 Ahsen Ejaz, Vassilis Papaefstathiou, and Ioannis Sourdis, “DDRNoC: Dual Data-Rate Network-on-Chip”, ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 2, June 2018.
• J8 M. Waqar Azhar, Per Stenström, and Vassilis Papaefstathiou, “SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures”, ACM Transactions on Architecture and Code Optimization (TACO), Volume 14, Issue 4, December 2017.
• J7 R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero, A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Pisani, F. Simula, P. Vicini, J. Navaridas, F. Chaix, N. Chrysos, M. Katevenis and V. Papaefstathiou, “Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project”, Journal of Physics: Conference Series, Volume 898, no. 8, p. 082045, November 2017.
• J6 Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, and Per Stenström, “Runtime-Assisted Global Cache Management for Task-based Parallel Programs”, IEEE Computer Architecture Letters (CAL), Volume 16, Issue 2, Pages 145–148, February 2017.
• J5 Spyros Lyberis, George Kalokerinos, Michael Lygerakis, Vassilis Papaefstathiou, Iakovos Mavroidis, Manolis Katevenis, Dionisios Pnevmatikatos, and Dimitrios S. Nikolopoulos. “FPGA Prototyping of Emerging Manycore Architectures for Parallel Programming Research using Formic Boards”, Elsevier Journal of Systems Architecture (JSA), Volume 60, Issue 6, Pages 481–493, June 2014.
• J4 Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Stamatis Kavadias, and Manolis Katevenis, “NP-SARC: Scalable Network Processing in the SARC Multi-core FPGA platform”, Elsevier Journal of Systems Architecture (JSA), Volume 59, Issue 1, Pages 39-47, January 2013.
• J3 Manolis Katevenis, Vassilis Papaefstathiou, Stamatis Kavadias, Dionisios Pnevmatikatos, Federico Silla, and Dimitrios S. Nikolopoulos, “Explicit Communication and Synchronization in SARC”, IEEE Micro Magazine (IEEE Micro), Volume 30, Issue 5, European Multicore Processing Projects, Pages 30-41, October 2010.
• J2 George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Manolis Katevenis, Dionisios Pnevmatikatos, and Xiaojun Yang, “Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability”, Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), Volume 5, Issue 3, SAMOS2009 Best Papers, October 2010.
• J1 Ioannis Papaefstathiou, Vassilis Papaefstathiou, and Christos Sotiriou, “Design-Space Exploration of the most widely used Cryptography Algorithms”, Elsevier Journal of Microprocessors and Microsystems (MICPRO), Volume 28, Issue 10, Secure Computing Platforms, Pages 561-571, December 2004.

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Peer-Reviewed Conference and Workshop Full Papers

• C35 Michalis Gianioudis, Pantelis Xirouchakis, Charisios Loukas, Evangelos Mageiropoulos, Orestis Mousouros, Sokratis Mpartzis, Aggelos Ioannou, Vassilis Papaefstathiou, Manolis Katevenis, Nikolaos Chrysos, “Low-latency Communication in RISC-V Clusters”, Proc. of the 7th International Conference on High Performance Computing in Asia-Pacific Region (HPCAsia), Nagoya, Japan, 25-27 January 2024.
• C34 Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesus Labarta, and Filippo Mantovani, “Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V”, Proc. of the 2nd International Workshop on RISC-V for HPC - in conjunction with the International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Denver, Colorado, USA, 12-17 November 2023.
• C33 Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, and Jesus Labarta, “Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study”, Proc. of the 1st International Workshop on RISC-V for HPC - in conjunction with the International Conference on High Performance Computing (ISC High Performance), Hamburg, Germany, 21-25 May, 2023.
• C32 Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto Gonzalez, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vasilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, and Ioannis Papaefstathiou, “eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem”, Proc. of the 20th ACM International Conference on Computing Frontiers (CF), Bologna, Italy, 9-11 May 2023.
• C31 Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martinez, Adrià Armejach, Marc Casas, Alejandro Nocua, and Romain Dolbeau, “Multilevel simulation-based co-design of next generation HPC microprocessors”, International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS) – in conjunction with the International Conference for High Performance Computing, Networking, Storage and Analysis (SC), St. Louis, Missouri, USA,14-19 November 2021.
• C30 Antonis Psistakis, Nikolaos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Gianioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou and Manolis Katevenis, “PART: Pinning Avoidance in RDMA Technologies”, Proc. of the 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Hamburg, Germany, 24-25 September 2020.
• C29 Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, and Ioannis Sourdis, “Hybrid2: Combining Caching and Migration in Hybrid Memory Systems”, Proc. of the 26th IEEE Symposium on High Performance Computer Architecture (HPCA), San Diego, California, USA, 22-26 February 2020. HiPEAC Paper Award
• C28 Fabien Chaix, Aggelos Ioannou, Nick Kossifidis, Nikolaos Dimou, Georgios Ieronymakis, Manolis Marazakis, Vassilis Papaefstathiou, Vassilis Flouris, Michael Ligerakis, George Ailamakis, Theocharis Vavouris, Astrinos Damianakis, Manolis Katevenis, and Iakovos Mavroidis, “Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping”, In the 5th International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'19) - in conjunction with the International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Denver, Colorado, USA, 17 November, 2019.
• C27 David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Antonio Ragagnin, Luca Tornatore, Giuliano Taffoni, and Igor Coretti, “Direct N-body Application on Low-Power and Energy-Efficient Parallel Architectures”, Proc. of the International Conference on Parallel Computing (ParCo), Prague, Czech Republic, 10-13 September, 2019.
• C26 Manolis Ploumidis, Nikolaos Kallimanis, Marios Asiminakis, Nikos Chrysos, Pantelis Xirouchakis, Michalis Gianoudis, Leandros Tzanakis, Nikolaos Dimou, Antonis Psistakis, Panagiotis Peristerakis, Giorgos Kalokairinos, Vassilis Papaefstathiou and Manolis Katevenis, “Software and Hardware co-design for low-power HPC platforms”, 5th International Workshop on Communication Architectures for HPC, Big Data, Deep Learning and Clouds at Extreme Scale (ExaComm) - in conjunction with the International Conference on High Performance Computing (ISC High Performance), Frankfurt, Germany, 16-20 June, 2019.
• C25 Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, and Ioannis Sourdis, “LLC-guided Data Migration in Hybrid Memory Systems”, Proc. of the 33rd IEEE International Parallel & Distributed Processing Symposium (IPDPS), Rio de Janeiro, Brazil, 20-24 May, 2019.
• C24 Ahsen Ejaz, Vassilis Papaefstathiou, and Ioannis Sourdis, “FreewayNoC: a DDR NoC with Pipeline Bypassing”, Proc. IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Torino, Italy, 4-5 October 2018. Best Paper Finalist
• C23 Kyriakos Paraskevas, Nikolaos Chrysos, Vassilis Papaefstathiou, Pantelis Xirouchakis, Panagiotis Peristerakis, Michalis Giannioudis, and Manolis Katevenis, “Virtualized Multi-Channel RDMA with Software-Defined Scheduling”, Proc. of the 7th International Young Scientist Conference on Computational Science (YSC), Heraklion, Greece, 02-06 July 2018.
• C22 Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, and Ioannis Sourdis, “FusionCache: Using LLC Tags for DRAM Cache”, Proc. Design, Automation & Test in Europe (DATE), Dresden, Germany, 19-23 March 2018.
• C21 Dmitry Knyaginin, Vassilis Papaefstathiou, and Per Stenström, “ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness”, Proc. of the 24th IEEE Symposium on High Performance Computer Architecture (HPCA), Vienna, Austria, 24-28 February 2018. HiPEAC Paper Award
• C20 Alirad Malek, Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, and Ioannis Sourdis, “Odd-ECC: On-demand DRAM Error Correcting Codes”, Proc. International Symposium on Memory Systems (MEMSYS), Washington DC, USA, 2-5 October 2017.
• C19 Evangelos Vasilakis, Ioannis Sourdis, Vassilis Papaefstathiou, Antonis Psathakis, and Manolis Katevenis, “Modeling Energy-Performance Tradeoffs in ARM big.LITTLE Architectures”, Proc. of the 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki, Greece, 25 - 27 September 2017.
• C18 Dmitry Knyaginin, Vassilis Papaefstathiou, and Per Stenström, “Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories”, Proc. International Symposium on Memory Systems (MEMSYS), Washington DC, USA, 3-6 October 2016.
• C17 Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, and Per Stenström, “RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches”, Proc. of the 22nd IEEE Symposium on High Performance Computer Architecture (HPCA), Barcelona, Spain, 12-16 March 2016. HiPEAC Paper Award
• C16 Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, and Manuel Palomino, “ECOSCALE: Reconfigurable Computing and Runtime System for Future Exascale Systems”, Proc. Design, Automation & Test in Europe (DATE), Dresden, Germany, 14-18 March 2016.
• C15 Antonis Psathakis, Vassilis Papaefstathiou, Nikolaos Chrysos, Fabien Chaix, Evangelos Vasilakis, Dionisios Pnevmatikatos, and Manolis Katevenis, “A Systematic Evaluation of Emerging Mesh-like CMP NoCs”, Proc. 11th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Oakland, California, USA, 5-7 May 2015.
• C14 Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, and Dionisios Pnevmatikatos, “Design Space Exploration for Fair Resource-Allocated NoC Architectures”, Proc. IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS), Samos, Greece, 14-17 July 2014.
• C13 Antonis Papadogiannakis, Laertis Loutsis, Vassilis Papaefstathiou, and Sotiris Ioannidis, “ASIST: Architectural Support for Instruction Set Randomization”, Proc. 20th ACM Conference on Computer and Communications Security (CCS), Berlin, Germany, 4-8 November 2013.
• C12 Vassilis Papaefstathiou, Manolis Katevenis, Dimitrios S. Nikolopoulos, and Dionisios Pnevmatikatos, “Prefetching and Cache Management Using Task Lifetimes”, Proc. 27th ACM International Conference on Supercomputing (ICS), Eugene, Oregon, USA, 10-14 June 2013.
• C11 Spyros Lyberis, George Kalokerinos, Michael Lygerakis, Vassilis Papaefstathiou, Dimitris Tsaliagkos, Manolis Katevenis, Dionisios Pnevmatikatos, and Dimitrios S. Nikolopoulos, “Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures”, Proc. IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Toronto, Canada, April 29 - May 1 2012. HiPEAC Paper Award
• C10 Pranav Tendulkar, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Dimitrios S. Nikolopoulos, and Manolis Katevenis, “Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives”, Proc. Design, Automation & Test in Europe (DATE), Grenoble, France, 14-18 March 2011.
• C9 Christoforos Kachris, George Nikiforos, Stamatis Kavadias, Vassilis Papaefstathiou, and Manolis Katevenis, “Network processing in Multi-core FPGAs with Integrated Cache-Network Interface”, Proc. IEEE International Conference on Reconfigurable Computing and FPGAs (Reconfig), Cancun, Mexico, 13-15 December 2010.
• C8 George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Manolis Katevenis, Dionisios Pnevmatikatos, and Xiaojun Yang, “FPGA Implementation of a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability”, Proc. IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS), Samos, Greece, 20-23 July 2009.
• C7 Vassilis Papaefstathiou, Dionisios Pnevmatikatos, Manolis Marazakis, George Kalokerinos, Angelos Ioannou, Michael Papamichael, Stamatis Kavadias, George Mihelogiannakis, and Manolis Katevenis, “Prototyping Efficient Interprocessor Communication Mechanisms”, Proc. IEEE International Symposium on Systems, Architectures, Modeling and Simulation (IC-SAMOS), Samos, Greece, 21-24 July 2007.
• C6 Manolis Marazakis, Vassilis Papaefstathiou, and Angelos Bilas, “Optimization and Bottleneck Analysis of Network Block I/O in Commodity Storage Systems”, Proc. 21th ACM International Conference on Supercomputing (ICS), Seattle Washington, USA, 16-20 June 2007.
• C5 Ioannis Papaefstathiou and Vassilis Papaefstathiou, “Memory Efficient 5-D Packet Classification at 40Gbps”, Proc. 26th IEEE Conference on Computer Communications (INFOCOM), Anchorage, Alaska, USA, 6-12 May 2007.
• C4 Manolis Marazakis, Konstantinos Xinidis, Vassilis Papaefstathiou, and Angelos Bilas, “Efficient Remote Block-level I/O over an RDMA-capable NIC”, Proc. 20th ACM International Conference on Supercomputing (ICS), Queensland, Australia, 28 June – 1 July 2006.
• C3 Vassilis Papaefstathiou and Ioannis Papaefstathiou, “An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks”, Proc. IEEE International Conference on Communications (ICC), Istanbul, Turkey, 11-15 June 2006.
• C2 Vassilis Papaefstathiou and Ioannis Papaefstathiou, “A Hardware-Engine for Layer-2 classification in low-storage, ultra-high bandwidth environments”, Proc. Design Automation & Test in Europe (DATE), Munich, Germany, 6-10 March 2006.
• C1 Vassilis Papaefstathiou and Ioannis Papaefstathiou, “A Memory Efficient, 100 Gb/sec MAC Classification Engine”, Proc. 30th IEEE Conference on Local Computer Networks (LCN), Sydney, Australia, 15-17 November 2005.

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Other Peer-Reviewed Short Papers and Posters

• O6 Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, and Dionisios Pnevmatikatos, “Design Trade-offs in Energy Efficient NoC Architectures”, Short Paper and Poster in 8th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Ferrara, Italy, 17-19 September 2014.
• O5 Christoforos Kachris, George Nikiforos, Stamatis Kavadias, Vassilis Papaefstathiou, and Manolis Katevenis, "Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters", Short Paper and Poster in IEEE International Conference on Cluster Computing (CLUSTER), Heraklion, Greece, 20-24 September 2010.
• O4 George Nikiforos, George Kalokerinos, Vassilis Papaefstathiou, Stamatis Kavadias, Dionisios Pnevmatikatos, and Manolis Katevenis, "A run-time Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability", In the 6th HiPEAC Industrial Workshop on Embedded Computing, THALES Research and Development - Palaiseau, Paris, France, 26 November 2008.
• O3 Vassilis Papaefstathiou, George Kalokerinos, Angelos Ioannou, Michael Papamichael, George Mihelogiannakis, Stamatis Kavadias, Evangelos Vlahos, Dionisios Pnevmatikatos, and Manolis Katevenis, “An FPGA-based Prototyping Platform for Research in High-Speed Interprocessor Communication”, In the 2nd HiPEAC Industrial Workshop on Embedded Computing, Philips (NXP) - Eindhoven, Netherlands, 17 October 2006.
• O2 Manolis Marazakis, Vassilis Papaefstathiou, George Kalokerinos and Angelos Bilas, “Experiences from Debugging a PCI-X-based RDMA-capable NIC”, In the 3rd Workshop on Remote Direct Memory Access (RDMA): Applications, Implementations, and Technologies (RAIT) in conjunction with IEEE International Conference on Cluster Computing (CLUSTER), Barcelona, Spain, 25-28 September 2006.
• O1 Vassilis Papaefstathiou and Ioannis Papaefstathiou, “A low-cost MAC Classification Engine”, Proc. 10th Panhellenic Conference on Informatics (PCI), Volos, Greece, 11-13 November 2005.

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Technical Reports and Theses

• TR2 Carlos Villavieja, Manolis Katevenis, Nacho Navarro, Dionisios Pnevmatikatos, Alex Ramirez, Stamatis Kavadias, Vassilis Papaefstathiou, and Dimitrios S. Nikolopoulos, “Hardware Support for Explicit Communication in Scalable CMP's”, UPC-BSC and FORTH-ICS, Technical Report UPC-DAC-RR-CAP-2009-1, January 2009.
• TR1 George Kalokerinos, Vassilis Papaefstathiou, Angelos Ioannou, Manolis Marazakis, Angelos Bilas, and Manolis Katevenis, “Design and Implementation of a Multi-Gigabit NIC and a Scalable Buffered Crossbar Switch”, FORTH-ICS, Technical Report 376, Heraklion, Greece, April 2006.
• PHD Vassilis Papaefstathiou, “Architectural Support for Software-Guided Energy Reduction of Manycore Communication”, Ph.D. Thesis, Computer Science Department, University of Crete, Greece, November 2013.
• MSC Vassilis Papaefstathiou, “Design and Implementation of Network Packet Classification Engines”, M.Sc. Thesis, Computer Science Department, University of Crete, Heraklion, Greece, March 2005.
• BSC Vassilis Papaefstathiou, “Design and Implementation of a Gamma Correction IP Block for a Digital TV SoC”, B.Sc. Thesis, Computer Science Department, University of Crete, Heraklion, Greece, June 2002.

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Other Unrefereed

• U9 Antonis Psistakis, Panagiotis Peristerakis, Pantelis Xirouchakis, Michalis Gianioudis, Giorgos Kalokairinos, Nikos Chrysos, Fabien Chaix, Vassilis Papaefstathiou, and Manolis Katevenis, “User-level RDMA with IOMMU Support on ARM Platforms”, Poster presented at the 14th HiPEAC Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), Fiuggi, Italy, 8-14 July 2018.
• U8 Pantelis Xirouchakis, Panagiotis Peristerakis, Michalis Gianoudis, Antonis Psistakis, Giorgos Kalokerinos, Nikos Chrysos, Vassilis Papaefstathiou, and Manolis G.H. Katevenis, “Low Latency RDMA for High-Performance Computing on ARM Platforms”, Poster presented at the 13th HiPEAC Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), Fiuggi, Italy, 10-14 July 2017
• U7 Konstantinos Harteros, Iakovos Mavroidis, George Kalokerinos, Vassilis Papaefstathiou, John Goodacre, Angelos Bilas, and Manolis G.H. Katevenis, “10GigE Virtualized NIC on ARM based FPGAs”, Poster presented at the 10th HiPEAC Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), Fiuggi, Italy, 13-19 July 2014.
• U6 Vassilis Papaefstathiou, Risat Pathan, Miquel Pericàs, and Per Stenström, “ERC Project MECCA: First retreat”, In the Spotlight, HiPEAC Newsletter, HiPEACinfo 39, July 2014.
• U5 Vassilis Papaefstathiou, “Architectural Support for Software-Guided Energy Reduction of Manycore Communication”, PhD News, HiPEAC Newsletter, HiPEACinfo 38, April 2014.
• U4 Vassilis Papaefstathiou and Michael Papamichael (In collaboration with Stamatis Kavadias, George Kalokerinos, Dionisios Pnevmatikatos, and Manolis Katevenis), “Interprocessor Communication: Towards Cache Integrated Network Interfaces”, Poster presented at the 3rd HiPEAC Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), L' Aquila, Italy, 15-20 July 2007.
• U3 Manolis Marazakis, Vassilis Papaefstathiou, and Angelos Bilas, “Performance Issues and Optimizations for Block-level Network Storage”, Poster presented at the 3rd HiPEAC Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), L' Aquila, Italy, 15-20 July 2007.
• U2 Vassilis Papaefstathiou, George Kalokerinos, Angelos Ioannou, Michael Papamichael, George Mihelogiannakis, Stamatis Kavadias, Evangelos Vlahos, Dionisios Pnevmatikatos, and Manolis Katevenis, “An FPGA-based Prototyping Platform for Research in High-Speed Interprocessor Communication”, Poster presented at the 2006 Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN), Stanford California, USA, 6-7 December 2006.
• U1 Manolis Marazakis, Konstantinos Xinidis, Vassilis Papaefstathiou, and Angelos Bilas, “High-Speed Block-level I/O over RDMA-capable NICs”, Poster presented at the 2006 Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN), Stanford California, USA, 6-7 December 2006.