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© copyright University of Crete, Greece.
Dept. of Computer Science, University of Crete.
CS-534: Packet Switch Architecture

5. Switch Queueing Architectures & Performance


Subsections in the current document:


5.1 Introduction: Switching Elements & Buffering Options



5.2 Output Queueing and Variations:


Output Queueing and Variations


5.3 Input Queueing and Variations:



5.4 Queueing Architecture Comparisons:



5.5 Performance of Input Queueing:



5.6 Scheduling for Input Buffered Switches:



[ Up to the Home Page of CS-534 ]
© copyright University of Crete, Greece.
Last updated: March 1998, by M. Katevenis.