CS523: Digital Circuits Design Lab Using EDA Tools (Spring 2018)
Department of Computer Science, University of Crete
Schedule
Class hours: Monday and Wednesday 14.15 - 16.00 in room H.206
Friday classes will be held as needed in room H.206 (14:15 - 16:00) to make up in case of instructor's absence during regular class meeting times.
Office hours: By Appointment
Staff
| Instructors | Teaching Assistants |
| Dr. Vassilis Papaefstathiou | Mr. Michalis Giaourtas |
| Prof. Manolis Katevenis | Mr. Theocharis Vavouris |
Course Information
| Area: | Microelectronic Systems Architecture (A) - M.Sc. Program |
| Description: | Electronic Design Automation (EDA) flows and Computer Aided Design (CAD) tools for digital circuit design. Advanced features of Hardware Description Languages (Verilog, VHDL). Behavioral and structural models. Simulation: algorithms and tools. Timing analysis. Design verification: input stimuli, output checking, simulations with models at different abstraction levels. Digital circuit testing and design for testability (DFT). Synthesizable description and logic synthesis tools (e.g. Xilinx Vivado, Synopsys Design Compiler). Placement and Routing: tools and techniques. Incremental design flows (back-annotation, ECO, LVS). Examples on FPGA and ASIC technologies. Using available IP cores to build System-on-Chip (SoC). Laboratory assignments on designing and verifying digital systems of medium complexity using the presented tools and flows for multiple target technologies (FPGA and ASIC). |
| ECTS: | 6 |
| Prerequisites: |
CS220 - Digital Circuits Lab
CS225 - Computer Organization |
| Grading: |
Lab Assignments: 30%
Project: 60% Class Participation: 10% |
| Mailing-list: | hy523-list at csd dot uoc dot gr |
We deeply appreciate the strong support provided to this course by the Computer Architecture and VLSI Systems (CARV) Laboratory of the Institute of Computer Science of FORTH through human resources and training of students on state-of-the-art EDA tools.
Lectures Schedule (Tentative)
| Date | Description | Material | Reading List |
|---|---|---|---|
| Week 01: 05 Feb. - 09 Feb. 2018 | Introduction to Design Flows | ||
| Week 02: 12 Feb. - 16 Feb. 2018 | Hardware Description Languages (SystemVerilog) | ||
| Week 03: 19 Feb. - 23 Feb. 2018 | Advanced HDL Features (SystemVerilog) | ||
| Week 04: 26 Feb. - 02 Mar. 2018 | No classes | ||
| Week 05: 05 Mar. - 09 Mar. 2018 | Simulation: Algorithms and Tools | ||
| Week 06: 12 Mar. - 16 Mar. 2018 | Logic Synthesis | ||
| Week 07: 19 Mar. - 23 Mar. 2018 | Static Timing Analysis | ||
| Week 08: 26 Mar. - 30 Mar. 2018 | Design for Testability | ||
| 02 Apr. - 15 Apr. 2018 | Easter Holiday Weeks | ||
| Week 09: 16 Apr. - 20 Apr. 2018 | Floorplanning and Power Planning | ||
| Week 10: 23 Apr. - 27 Apr. 2018 | Placement | ||
| Week 11: 30 Apr. - 04 May 2018 | Routing | ||
| Week 12: 07 May. - 11 May 2018 | Power Optimization | ||
| Week 13: 14 May. - 18 May 2018 | Physical Verification |
Laboratory Assignments (Tentative)
| Date | Description | Material | Deadline |
|---|---|---|---|
| Week 03: 19 Feb. - 23 Feb. 2018 | Lab 1: SystemVerilog Testbenches | Week 06: 12 Mar. - 16 Mar. 2018 | |
| Week 06: 12 Mar. - 16 Mar. 2018 | Lab 2: Logic Synthesis | Week 08: 26 Mar. - 30 Mar. 2018 | |
| Week 09: 16 Apr. - 20 Apr. 2018 | Lab 3: Physical Design and Implementation | Week 12: 07 May - 11 May 2018 | |
| Week 10: 23 Apr. - 27 Apr. 2018 | Student Projects | Week 13: 14 May - 18 May 2018 |
Last update: 5 Mar. 2018 - by V. Papaefstathiou